This application is based on Patent Application No. 2001-34324 filed Feb. 9, 2001 in Japan, the content of which is incorporated hereinto by reference.
1. Field of the Invention
The present invention relates to a method for forming a recognition mark, for performing image recognition, on a substrate as a carrier for an IC socket for inspecting a KGD (Known Good Die, namely, a good bare chip satisfying a specification). More particularly, the invention relates to a method for forming a recognition mark on a substrate in such a manner that the recognition mark can be recognized from a back surface (a surface not formed with a wiring pattern) of the substrate formed with a wiring pattern on one side.
2. Description of the Related Art
In the recent years, for higher package density on a circuit board and higher speed, it is becoming typical to surface mount a plurality of bare (namely, before packaging) LSI chips. From this, it is necessary to inspect the chip by mounting the base chip on an IC socket.
For the purpose of inspection, it is difficult to directly mount the chip on the IC socket. Therefore, a substrate as a bare chip carrier is employed.
The substrate is formed by forming a conductive wiring (wiring pattern) of copper or the like on a film form insulating substrate of polyimide or the like, namely, on a flexible insulating substrate. The wiring pattern is formed on the insulating substrate in such a manner that a conductive layer, which is formed by bonding of a conductive foil or plating, is processed to establish a predetermined wiring pattern by etching or the like.
On the substrate as set forth above, a recognition mark for performing image recognition or other processes depending upon application thereof is provided. The recognition mark is typically formed at the same time as formation of the wiring pattern with the conductive layer forming the wiring pattern.
However, in the flexible substrate, a bump can be formed on the back surface (the surface where the wiring pattern is not formed) for the purpose of electrical connection with the bare chip as exemplarily illustrated in FIGS. 5A and 5B. In the bump forming process shown in FIGS. 5A and 5B, the bump 4 is formed through the following processes. (1) At portions to form the bumps 4, holes 3 are formed in the insulating substrate 1 by laser machining from the back surface 5 of the insulating substrate where the conductive pattern is not formed (see FIG. 5A). (2) Subsequently, with resisting and plating on the insulating substrate 1, plating is selectively grown only in the portions where the holes 3 are formed to form the bumps 4 (see FIG. 5B).
As set forth above, in the substrate formed with the bumps on the back surface, the bare chip to be inspected is naturally mounted on the back surface of the substrate. Therefore, it is required for the recognition mark to be provided on the back surface of the substrate.
As a conventional method for forming the recognition mark on the back surface of the substrate, the following processes have been considered, for example:
(1) a method using an insulating substrate 1 having conductive layers on both surfaces, wherein the recognition mark 6 is formed by etching the conductive layer on the back surface 5 in similar process to formation of the wiring pattern 2 (see FIGS. 6A and 6B); and
(2) a method for forming the insulating substrate of a transparent material, and then forming the recognition mark 6 together with the wiring pattern (see FIGS. 7A and 7B).
However, in case of the substrate formed with the recognition mark by the method of (1), while no problems will be encountered in using the substrate for inspecting the chip, the conductive layers are required on both surfaces of the insulating substrate. Also, two etching steps, for the front surface and the back surface, are required in a fabrication process. Thereby inherently raising of manufacturing costs.
In case of the substrate formed with the recognition mark by the method of (2), while no problems will be encountered as long as the insulating substrate is kept transparent, the insulating substrate may be tarnished by being exposed in a high temperature atmosphere resulting in difficulties in recognition. Particularly, when inspecting the KGD, since the substrate has to be exposed in a high temperature atmosphere for a long period, the substrate is not suitable for repeated use as the KGD carrier.
The present invention has been worked out for solving the drawbacks in the prior art set forth above. Therefore, it is an object of the present invention to provide a method for forming a recognition mark on a back surface of a substrate which can be fabricated in reduced manufacturing cost, is easy to manufacture and permits repeated use of the substrate formed with the recognition mark.
In order to achieve the above object of the present invention, a method for forming a recognition mark on a substrate for a KGD, wherein wiring patterns are formed on a surface of one side of an insulating substrate, is featured as comprising the following steps. The first step is forming a conductive pattern as a recognition mark on one surface where the wiring patterns are formed. The second step is forming a through hole from a surface where the wiring pattern is not formed toward the conductive pattern.
In a method for forming a recognition mark on a substrate for a KGD, the substrate is formed with a bump to be connected to the KGD on the surface where the wiring pattern is not formed.
In a method for forming a recognition mark on a substrate for a KGD, the conductive pattern may also have a particular shape as the recognition mark. Alternatively, in a method for forming a recognition mark on a substrate for a KGD, a shape of the through hole may define the recognition mark.
Further, a method for forming a recognition mark on a substrate for a KGD can be applied to the substrate that wiring patterns are formed on a plurality of layers of an insulating substrate.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings.